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HS-80C85RH
February 1996
Radiation Hardened 8-Bit CMOS Microprocessor
Description
The HS-80C85RH is an 8-bit CMOS microprocessor fabricated using the Intersil radiation hardened self-aligned junction isolated (SAJI) silicon gate technology. Latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices. The HS-80C85RH is a functional logic emulation of the HMOS 8085 and its instruction set is 100% software compatible with the HMOS device. The HS80C85RH is designed for operation with a single 5 volt power supply. Its high level of integration allows the construction of a radiation hardened microcomputer system with as few as three ICs (HS80C85RH CPU, HS83C55RH ROM I/O, and the HS-81C55/ 56RH RAM I/O.
Features
* Devices QML Qualified in Accordance With MIL-PRF-38535 * Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95824 and Intersil' QM Plan * Radiation Hardened EPI-CMOS - Parametrics Guaranteed 1 x 105 RAD(Si) - Transient Upset > 1 x 108 RAD(Si)/s - Latch-up Free > 1 x 1012 RAD(Si)/s * Low Standby Current 500A Max * Low Operating Current 5.0mA/MHz (X1 Input) * Electrically Equivalent to Sandia SA 3000 * 100% Software Compatible with INTEL 8085 * Operation from DC to 2MHz, Post Radiation * Single 5 Volt Power Supply * On-Chip Clock Generator and System Controller * Four Vectored Interrupt Inputs * Completely Static Design * Self Aligned Junction Isolated (SAJI) Process * Military Temperature Range -55oC to +125oC
Pinouts
40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835, CDIP2-T40 TOP VIEW
X1 1 X2 2 RESET OUT 3 SOD 4 SID 5 TRAP 6 RST 7.5 7 RST 6.5 8 RST 5.5 9 INTR 10 INTA 11 AD0 12 AD1 13 AD2 14 AD3 15 AD4 16 AD5 17 AD6 18 AD7 19 GND 20 40 VDD 39 HOLD 38 HLDA 37 CLOCK OUT 36 RESET IN 35 READY 34 IO / M 33 S1 32 RD 31 WR 30 ALE 29 S0 28 A15 27 A14 26 A13 25 A12 24 A11 23 A10 22 A9 21 A8 X1 X2 RESET OUT SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA AD0 AD1 AD2 AD3 AD4 NC NC AD5 AD6 AD7
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) INTERSIL OUTLINE K42.A TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD HOLD HLDA CLOCK OUT RESET IN READY IO / M S1 RD WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8 GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
1
518054 3036.2
HS-80C85RH Ordering Information
PART NUMBER 5962R9582401QQC 5962R9582401QXC 5962R9582401VQC 5962R9582401VXC HS1-80C85RH/SAMPLE HS9-80C85RH/SAMPLE TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC -55oC to +125oC -55oC to +125oC +25oC +25oC SCREENING LEVEL MIL-PRF-38535 Level Q MIL-PRF-38535 Level Q MIL-PRF-38535 Level V MIL-PRF-38535 Level V Sample Sample PACKAGE 40 Lead SBDIP 42 Lead Ceramic Flatpack 40 Lead SBDIP 42 Lead Ceramic Flatpack 40 Lead SBDIP 42 Lead Ceramic Flatpack
Functional Diagram
INTA INTR RST 5.5 RST 6.5 RST 7.5 TRAP SID SOD
INTERRUPT CONTROL
SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS
ACCUMULATOR (8)
TEMP REG (8)
FLAG (5) FLIP FLOPS
INSTRUCTION REGISTER (8)
B REG (8) D REG (8) H REG (8)
C REG (8) REGISTER ARRAY DATA ADDRESS BUFFER (8) AD1-AD0 ADDRESS BUS E REG (8) L REG (8)
ARITHMETIC LOGIC UNIT (ALU) (8) POWER SUPPLY X1 X2 VDD GND CLK GEN
INSTRUCTION DECODER AND MACHINE CYCLE ENCODING
STACK POINTER (16) PROGRAM COUNTER (16) INCREMENTER DECREMENTER ADDRESS LATCH (16)
TIMING AND CONTROL CONTROL STATUS DMA
RESET
ADDRESS BUFFER (8)
READY CLK OUT RD
WR ALE
S0 S1
IO/M HOLD
HLDA RESET IN
RESET OUT
A15-A8 ADDRESS BUS
Spec Number 2
518054
HS-80C85RH Pin Description
SYMBOL A8 - A15 PIN NUMBER 21-28 TYPE O DESCRIPTION Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address, 3-stated during Hold and Halt modes and during RESET. Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second and third clock cycles. Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the address to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. The falling edge of ALE can also be used to strobe the status information. ALE is never 3-stated. Machine Cycle Status: IO/M 0 0 1 1 0 1 1 T T T S1 0 1 0 1 1 1 1 0 X X S0 1 0 1 0 1 1 1 0 X X Status Memory write Memory write I/O write I/O read Opcode fetch Opcode fetch Interrupt acknowledge Halt Hold Reset
AD0-7
12-19
I/O
ALE
32
O
S0, S1, and IO/M
31, 35, & 36
O
T = 3-State (high impedance) X = Unspecified S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of these lines. RD 34 O Read Control: A low level on RD indicates the selected memory or I/O device is to be read and that the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RESET. Write Control: A low level on WR indicates the data on the Data Bus is to be written into the selected memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and Halt modes and during RESET. Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If READY is low, the cpu will wait an integral number of clock cycles for READY to go high before completing the read or write cycle. READY must conform to specified setup and hold times. Hold: Indicates that another master is requesting the use of the address and data buses. The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer. Internal processing can continue. The processor can regain the bus only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data Bus, RD, WR, and IO/M lines are 3-stated. Hold Acknowledge: Indicates that the cpu has received the HOLD request and that it will relinquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The cpu takes the bus one half clock cycle after HLDA goes low.
WR
33
O
READY
35
I
HOLD
39
I
HLDA
38
O
Spec Number 3
518054
HS-80C85RH Pin Description
SYMBOL INTR (Continued)
PIN NUMBER 10
TYPE I
DESCRIPTION Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some other interrupt port. Restart Interrupts: These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted. The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher priority than INTR. In addition, they may be individually masked out using the SIM instruction. Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt. (See Table 6.) Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops. The data and address buses and the control lines are 3-stated during RESET and because of the asynchronous nature of RESET the processor's internal registers and flags may be altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connection to an R-C network for power-on RESET delay (see Figure 1). Upon power-up, RESET IN must remain low for at least 10 "clock cycle" after minimum VDD has been reached. For proper reset operation after the power-up duration, RESET IN should be kept low a minimum of three clock periods. The CPU is held in the reset condition as long as RESET IN is applied. Reset Out: Reset Out indicates cpu is being reset. Can be used as a system reset. The signal is synchronized to the processor clock and lasts an integral number of clock periods. X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator. X, can also be an external clock Input from a logic gate. The input frequency is divided by 2 to give the processor's internal operating frequency. Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period. Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction. Power: +5V supply. Ground: Reference.
INTA
11
O
RST 5.5 RST 6.5 RST 7.5
9 8 7
I
TRAP
6
I
RESET IN
36
I
RESET OUT
3
O
X1 X2
1 2
I O
CLK
37
O
SID
5
I
SOD VCC GND
4 40 20
O I I
RESET IN R1 VDD TYPICAL POWER-ON RESET RC VALUES R1 = 75K C1 = 1F C1
Values may have to vary due to applied power supply ramp up time.
FIGURE 1. POWER-ON RESET CIRCUIT
Spec Number 4
518054
Specifications HS-80C85RH
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC Typical Derating Factor. . . . . . . . . . .2.0mA/MHz Increase in IDDOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 45oC/W 10oC/W Ceramic Flatpack Package . . . . . . . . . . . 77oC/W 13oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.65W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . 13.0mW/oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage Range (VDD) . . . . . . . +4.75V to +5.25V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -0.5V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 7, 8A, 8B LIMITS TEMPERATURE -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC MIN -1.0 VDD -0.5 MAX 1.0 0.5 500 5.0 UNITS A V V A mA/MHz -
PARAMETER Input Leakage Current High Level Output Voltage Low Level Output Voltage Static Current Operating Supply Current (Note 2) Functional Tests
SYMBOL IIH or IIL VOH VOL IDDSB IDDOP FT
CONDITIONS VDD = 5.25V, VI = VDD or GND VDD = 4.75V, IOH = -1.0mA VDD = 5.25V, IOL = 1.0mA, VDD = 5.25V, Clock Out = Hi and Low VDD = 5.25V, f = 1MHz (Note 2) VDD = 4.75V and 5.25V, TCYC = 500ns, VOL VDD/2, VOH VDD/2
NOTES: 1. All devices guaranteed at worst case limits and over radiation. 2. Operating supply current (IDDOP) is proportional to crystal frequency. Parts are tested at 1MHz TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 LIMITS TEMPERATURE -55oC, -55oC, -55oC, -55oC, -55oC, -55oC, -55oC, -55oC, -55oC, -55oC, +25oC, +25oC, +25oC, +25oC, +25oC, +25oC, +25oC, +25oC, +25oC, +25oC, +125oC +125oC +125oC +125oC +125oC +125oC +125oC +125oC +125oC +125oC MIN 40 100 30 50 300 300 875 MAX 115 115 250 275 70 UNITS ns ns ns ns ns ns ns ns ns ns
PARAMETER CLK Low Time (Standard CLK Loading) CLK High Time (Standard CLK Loading) CLK Rise Time CLK Fall Time X1 Rising to CLK Rising X1 Rising to CLK Falling A8-15 Valid to Leading Edge of Control (Note 5) A0-7 Valid to Leading Edge of Control A0-15 Valid to Valid Data In Address Float After Leading Edge of READ (INTA)
SYMBOL T1 T2 Tr Tf TXKR TXKF TAC TACL TAD TAFR
Spec Number 5
518054
Specifications HS-80C85RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 LIMITS TEMPERATURE -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC MIN 75 125 250 150 575 60 575 90 75 150 125 675 200 120 375 550 250 150 MAX 375 375 0 300 0 375 350 175 0 0 50 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER A8-15 Valid Before Trailing Edge of ALE (Note 5) A0-7 Valid Before Trailing Edge of ALE READY Valid from Address Valid Address (A8-15) Valid After Control Width of Control Low (RD, WR, INTA) Edge of ALE Trailing Edge of Control to Leading Edge of ALE Data Valid to Trailing Edge of WRITE HLDA to Bus Enable Bus Float After HLDA HLDA Valid to Trailing Edge of CLK HOLD Hold Time HOLD Setup Time to Trailing Edge of CLK INTR Hold Time INTR, RST and TRAP Setup Time to Falling Edge of CLK Address Hold Time After ALE Trailing Edge of ALE to Leading Edge of Control ALE Low During CLK High ALE to Valid Data During Read ALE to Valid Data During Write ALE Width ALE to READY Stable Trailing Edge of READ to Re-Enabling the Address READ (or INTA) to Valid Data Control Trailing Edge to Leading Edge of Next Control Data Hold Time After READ INTA READY Hold Time READY Setup Time to Leading Edge of CLK Data Valid After Trailing Edge of WRITE LEADING Edge of WRITE to Data Valid NOTES:
SYMBOL TAL tALL TARY TCA TCC TCL TDW THABE THABF THACK THDH THDS TINH TINS TLA TLC TLCK TLDR TLDW TLL TLRY TRAE TRD TRV TRDH TRYH TRYS TWD TWDL
-55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, -55oC, -55oC, -55oC, -55oC, -55oC, -55oC, +25oC, +25oC, +25oC, +25oC, +25oC, +25oC, +25oC, +125oC +125oC +125oC +125oC +125oC +125oC +125oC
-55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, -55oC, -55oC, -55oC, +25oC, +25oC, +25oC, +25oC, +125oC +125oC +125oC +125oC
1. Output timings are measured with a purely capacitive load, CL = 150pF 2. VDD = 4.75V, VIH = 4.25V, VIL = 0.8V 3. Delay times are measured with a 1MHz clock. An algorithm is used to convert the delays into the AC timings above with a TCYC = 500ns. 4. The AC table is tested as shown above to guarantee the processor system timing. 5. A8 - A15 address specifications also apply to IO/M, S0 and S1 except A8 - A15 are undefined during T4-T6 of off cycle whereas IO/M, So, and S1 are stable.
Spec Number 6
518054
Specifications HS-80C85RH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Input Capacitance I/O Capacitance Output Capacitance NOTE: 1. All measurements referenced to device ground. TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: The post irradiation test conditions and limits are the same as those listed in Tables 1 and 2. TABLE 5. BURN-IN DELTA PARAMETERS (+25oC; In Accordance With SMD) SYMBOL CIN CI/O COUT (NOTE 1) CONDITIONS VDD = Open, f = 1MHz VDD = Open, f = 1MHz VDD = Open, f = 1MHz TEMPERATURE TA = +25oC TA = +25oC TA = +25oC MIN MAX 12 13 12 UNITS pF pF pF
TABLE 6. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY ADDRESS BRANCHED TO (1) WHEN INTERRUPT OCCURS 24H 3CH 34CH 2CH See Note 2
NAME TRAP RST 7.5 RST 6.5 RST 5.5 INTR NOTES:
PRIORITY 1 2 3 4 5
TYPE TRIGGER Rising edge and high level until sampled. Rising edge (latched) High level until sampled. High level until sampled. High level until sampled.
1. The processor pushes the PC on the stack before branching to the indicated address. 2. The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged. TABLE 7. BUS TIMING SPECIFICATION AS A tCYC DEPENDENT SYMBOL tAL tLA tLL tLCK tLC tAD tRD tRAE tCA tDW tWD HS-8OC85RH (1/2)T- 175 (1/2)T- 175 (1/2)T-50 (1/2)T- 125 (1/2)T- 100 (5/2 + N)T - 375 (3/2 + N)T - 375 (1/2)T- 130 (1/2)T - 100 (3/2 + N)T - 175 (1/2)T-100 Minimum Minimum Minimum Minimum Minimum Maximum Maximum Minimum Minimum Minimum Minimum SYMBOL tCC tCL tARY tHACK tHABF tHABE tAC t1 t2 tRV tLDR HS-8OC85RH (3/2 + N)T - 175 (1/2)T - 190 (3/2)T - 500 (1/2)T - 160 (1/2)T +125 (1/2)T +125 (2/2)T - 200 (1/2)T-210 (1/2)T- 150 (3/2)T - 200 (4/2)T - 325 Minimum Minimum Maximum Minimum Maximum Maximum Minimum Minimum Minimum Minimum Maximum
NOTE: N is equal to the total WAIT states T = tCYC
Spec Number 7
518054
HS-80C85RH Waveforms
X1 INPUT
tr CLK OUTPUT tXKR tXKF t1 tCYC
t2
tf
FIGURE 2. CLOCK
T1 CLK tLCK A8-15 ADDRESS tAD AD0-AD7 tLL ALE tAL RD/INTA tAC tLC ADDRESS tLA tAFR
T2
T3
T1
tCA
tRAE tRDH DATA IN tCL tLDR tRD tCC
FIGURE 3. READ
T1 CLK tLCK A8-15 ADDRESS tLDW AD0-AD7 tLL ALE tAL ADDRESS tLA
T2
T3
T1
tCA DATA OUT tDW tWDL tCC tWD
WR tAC
tLC
tCL
FIGURE 4. WRITE
Spec Number 8
518054
HS-80C85RH Waveforms
(Continued)
T2 CLK T2 THOLD THOLD T1
HOLD tHDS HLDA tHDH tHACK
tHABF tHABE
BUS
(ADDRESS, CONTROLS)
FIGURE 5. HOLD
T1 CLK tLCK
T2
TWAIT
T3
T3
tCA A8-15 ADDRESS tAD AD0-AD7 tLL ALE tAL RD/INTA tAC tARY READY NOTE 1: READY MUST REMAIN STABLE DURING SETUP AND HOLD TIMES. tLC tLRY ADDRESS tLA tAFR tLDR tRD tCC tRDH DATA IN tCL tRAE
tRYS tRYH
tRYS tRYH
FIGURE 6. READ OPERATION WITH WAIT CYCLE (TYPICAL) - SAME READY TIMING APPLIES TO WRITE
T1
T2
T3
T4
T5
T6
THOLD T1
T2
A8-15 A0-7 CALL INST. BUS FLOATING
RD INTR INTR tINH tINS HOLD tHDH HLDA tHDS tHACK tHABF tHABE
IO/M IS ALSO FLOATING DURING THIS TIME.
FIGURE 7. INTERRUPT AND HOLD
Spec Number 9
518054
HS-80C85RH
TABLE 9. INSTRUCTION SET SUMMARY
INSTRUCTION CODE MNEMONIC D7 D6 D5 D4 D3 D2 D1 D0 OPERATIONS DESCRIPTION INSTRUCTION CODE MNEMONIC RNZ D D S S S Move register to register Move register to memory Move memory to register Move immediate register Move immediate memory Load immediate register Pair B & C Load immediate register Pair D & E Load immediate register Pair H & L Store A indirect Store A indirect Load A indirect Load A indirect Store A direct Load A direct Store H & L direct Load H & L direct Exchange D & E, H & L Registers POP B 1 1 0 0 0 0 0 1 INX D 0 0 0 1 0 0 1 1 RP RM RPE D7 1 1 1 1 D6 1 1 1 1 D5 0 1 1 1 D4 0 1 1 0 D3 0 0 1 1 D2 0 0 0 0 D1 0 0 0 0 D0 0 0 0 0 OPERATIONS DESCRIPTION Return on no zero Return on positive Return on minus Return on parity even Return on parity odd
MOVE, LOAD, AND STORE MOVr1, r2 0 1 D
MOV M.r
0
1
1
1
0
S
S
S
MOV r.M
0
1
D
D
D
1
1
0
RPO
1
1
1
0
0
0
0
0
MVl r
0
0
D
D
D
1
1
0
RESTART RST 1 1 A A A 1 1 1 Restart
MVl M
0
0
1
1
0
1
1
0
INPUT/OUTPUT IN OUT 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 1 Input Output
LXl B
0
0
0
0
0
0
0
1
LXl D
0
0
0
1
0
0
0
1
INCREMENT AND DECREMENT INR r DCR r INR M DCR M INX B 0 0 0 0 0 0 0 0 0 0 D D 1 1 0 D D 1 1 0 D D 0 0 0 1 1 1 1 0 0 0 0 0 1 0 1 0 1 1 Increment register Decrement register Increment memory Decrement memory Increment B & C registers Increment D & E registers Pop register Pair B & C off stack Pop register Pair D & E off stack Popregister Pair H & L off stack Pop A and Flags off stack Exchange top ot stack, H & L H & L to stack pointer Load immediate stack pointer Increment stack pointer Decrement stack pointer
LXl H
0
0
1
0
0
0
0
1
STAX B STAX D LDAX B LDAX D STA LDA SHLD LHLD XCHG
0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 1
0 1 0 1 1 1 0 0 0
0 0 1 1 0 1 0 1 1
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1
POP D
1
1
0
1
0
0
0
1
POP H
1
1
1
0
0
0
0
1
STACK OPS PUSH B 1 1 0 0 0 1 0 1 Push register Pair B & C on stack Push register Pair D & E on stack Push register Pair H & L on stack Push A and Flags on stack Call on zero Call on no zero Call on positive Call on minus Call on parity even Call on parity odd JUMP JMP JC JNC 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 Return Return on carry Return on no carry Return on zero JZ JNZ JP JM 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 POP PSW 1 1 1 1 0 0 0 1
PUSH D
1
1
0
1
0
1
0
1
XTHL
1
1
1
0
0
0
1
1
PUSH H
1
1
1
0
0
1
0
1
SPHL
1
1
1
1
1
0
0
1
PUSH PSW
1
1
1
1
0
1
0
1
LXI SP
0
0
1
1
0
0
0
1
CZ CNZ CP CM CPE CPO RETURN RET RC RNC RZ
1 1 1 1 1 1
1 1 1 1 1 1
0 0 1 1 1 1
0 0 1 1 0 0
1 0 0 1 1 0
1 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0 0 0
INX SP
0
0
1
1
0
0
1
1
DCX SP
0
0
1
1
1
0
1
1
Jump unconditional Jump on carry Jump on no carry Jump on zero Jump on no zero Jump on positive Jump on minus
Spec Number 10
518054
HS-80C85RH
TABLE 9. INSTRUCTION SET SUMMARY (Continued)
INSTRUCTION CODE MNEMONIC JPE D7 1 D6 1 D5 1 D4 0 D3 1 D2 0 D1 1 D0 0 OPERATIONS DESCRIPTION Jump on parity even Jump on parity odd H & L to program counter INSTRUCTION CODE MNEMONIC ADC M D7 1 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 OPERATIONS DESCRIPTION Add memory to A with carry Add immediate to A Add immediate to A with carry Add B & C to H & L Add D & E to H & L Add H & L to H & L Add stack pointer to H&L
JPO PCHL
1 1
1 1
1 1
0 0
0 1
0 0
1 0
0 1
ADl ACl
1 1
1 1
0 0
0 0
0 1
1 1
1 1
0 0
CALL CALL CC CNC LOGICAL ANA r XRA r 1 1 0 0 1 1 0 0 0 1 S S S S S S And register with A Exclusive OR register with A OR register with A Compare register with A And memory with A Exclusive OR memory with A OR memory with A Compare memory with A And immediate with A Exclusive OR immediate with A OR immediate with A Compare immediate with A 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 0 0 Call unconditional Call on carry Call on no carry
DAD B DAD D DAD H DAD SP
0 0 0 0
0 0 0 0
0 0 1 1
0 1 0 1
1 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
SUBTRACT SUB r 1 0 0 1 0 S S S Subtract register from A Subtract register from A with borrow Subtract memory from A Subtract memory from A with borrow Subtract immediate from A Subtract immediate from A with borrow
ORA r CMP r
1 1
0 0
1 1
1 1
0 1
S S
S S
S S
SBB r
1
0
0
1
1
S
S
S
SUB M
1
0
0
1
0
1
1
0
ANA M XRA M
1 1
0 0
1 1
0 0
0 1
1 1
1 1
0 0
SBB M
1
0
0
1
1
1
1
0
SUl
1
1
0
1
0
1
1
0
ORA M CMP M
1 1
0 0
1 1
1 1
0 1
1 1
1 1
0 0
SBl
1
1
0
1
1
1
1
0
ANI
1
1
1
0
0
1
1
0
SPECIALS CMA STC CMC DAA CONTROL El 1 1 0 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 0 Enable Interrupts Disable Interrupt No-operation Halt Read Interrupt Mask Set Interrupt Mask 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 Complement A Set carry Complement carry Decimal adjust A
XRI
1
1
1
0
1
1
1
0
ORl
1
1
1
1
0
1
1
0
CPl
1
1
1
1
1
1
1
0
ROTATE RLC RRC RAL 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 Rotate A left Rotate A right Rotate A left through carry Rotate A right through carry Increment H & L registers Decrement B & C Decrement D & E Decrement H & L
DI NOP HLT RIM
RAR
0
0
0
1
1
1
1
1
SlM
NOTES:
0
0
1
1
0
0
0
0
INX H
0
0
1
0
0
0
1
1
1. DDS or SSS: B000, C001, D010, E011, H100, L101, Memory 110, A111
DCX B DCX D DCX H ADD ADD r ADC r
0 0 0
0 0 0
0 0 1
0 1 0
1 1 1
0 0 0
1 1 1
1 1 1
2. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags.
All mnemonics copyrighted Intel Corporation 1976
1 1
0 0
0 0
0 0
0 1
S S
S S
S S
Add register to A Add register to A with carry Add memory to A
ADD M
1
0
C
0
0
1
1
0
Spec Number 11
518054
HS-80C85RH Functional Description
The HS-80C85RH is a complete 8-bit parallel central processing unit implemented in a self aligned, silicon gate, CMOS technology. Its static design allows the device to be operated at any external clock frequency from a maximum of 4MHz down to DC. The processor clock can be stopped in either the high or low state and held there indefinitely. This type of operation is especially useful for system debug or power critical applications. The device is designed to fit into a minimum system of three ICs: CPU (HS-80C85RH), RAM/ IO (HS-81C55/56RH) and ROM/IO Chip (HS-83C55RH). Since the HS-80C85RH is implemented in CMOS, all of the advantages of CMOS technology are inherent in the device. These advantages include low standby and operating power, high noise immunity, moderately high speed, wide operating temperature range, and designed-in radiation hardness. Thus the HS-80C85RH is ideal for weapons and space applications. The HS-80C85RH has twelve addressable 8-bit registers. Four of them can function only as two 16-bit register pairs. Six others can be used interchangeably as 8-bit registers or as 16-bit register pairs. The HS-80C85RH register set is as follows:
MNEMONIC ACC or A PC BC, DE, HL REGISTER Accumulator Program Counter General-Purpose Registers; Data Pointer(HL) Stack Pointer Flag Register CONTENTS 8 -bits 16-bit Address 8-bits x 6 or 16-bits x 3
enabled or disabled by El or Dl software instructions), and causes the CPU to fetch in an RST instruction, externally placed on the data bus, which vectors a branch to any one of eight fixed memory locations (Restart addresses). The decimal addresses of these dedicated locations are: 0, 8, 16, 24, 32, 40, 48, and 56. Any of these addresses may be used to store the first instruction(s) of a routine designed to service the requirements of an interrupting device. Since the (RST) is a call, completion of the instruction also stores the old program counter contents on the STACK. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a programmable mask. TRAP is also a RESTART interrupt but it is nonmaskable. The three maskable interrupts cause the internal execution of RESTART (saving the program counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART vector independent of the state of the interrupt enable or masks. (See Table 9.) There are two different types of inputs in the restart interrupts. RST 5.5 and RST 6.5 are high level-sensitive and are recognized with the same timing as INTR. RST 7.5 is rising edge sensitive. For RST 7.5, only a pulse is required to set an internal flipflop which generates the internal interrupt request (a normally high level signal with a low going pulse is recommended for highest system noise immunity). The RST 7.5 request flip-flop remains set until the request is serviced. Then it is reset automatically. This flip-flop may also be reset by using the SlM instruction or by issuing a RESET IN to the 80C85RH. The RST 7.5 internal flip-flop will be set by a pulse on the RST 7.5 pin even when the RST 7.5 interrupt is masked out. The status of the three RST interrupt masks can only be affected by the SIM instruction and RESET IN. The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if more than one is pending as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST 5.5, INTR-lowest priority. This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine if the interrupts are re-enabled before the end of the RST 7.5 routine. The TRAP interrupt is useful for catastrophic events such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive. The TRAP input must go high and remain high until it is acknowledged. It will not be recognized again until it goes low, then high again. This avoids any false triggering due to noise or logic glitches. Figure 8illustrates the TRAP interrupt request circuitry within the HS-80C85RH. Note that the servicing of any interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) disables all future interrupts (except TRAPs) until an EI instruction is executed.
SP Flags or F
16-bit Address 5 Flags (8-bit space)
The HS-80C85RH uses a multiplexed Data Bus. The address is split between the higher 8-bit Address Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a machine cycle the low order address is sent out on the Address/Data bus. These lower 8 bits may be latched externally by the Address Latch Enable signal (ALE). During the rest of the machine cycle the data bus is used for memory or I/O data. The HS-80C85RH provides RD, WR, S0, S1, and IO/M signals for bus control. An Interrupt Acknowledge signal (INTA) is also provided. HOLD and all Interrupts are synchronized with the processor's internal clock. The HS-80C85RH also provides Serial Input Data (SID) and Serial Output Data (SOD) lines for simple serial interface. In addition to these features, the HS-80C85RH has three maskable, vector interrupt pins, one nonmaskable TRAP interrupt, and a bus vectored interrupt, INTR. Interrupt and Serial I/O The HS-80C85RH has 5 interrupt inputs: INTR, RST 5.5, RST 6.5, RST 7.5, and TRAP INTR is maskable (can be
Spec Number 12
518054
HS-80C85RH
EXTERNAL INSIDE THE 80C85RH TRAP INTERRUPT TRAP REQUEST RESET IN TRAP SCHMITT TRIGGER RESET CLK D Q D F/F CLEAR INTERRUPT REQUEST
2. A 10M resistor is required between X1 and X2 for bias point stabilization. In addition, the crystal should have the following characteristics: 1) Parallel resonance at twice the desired internal clock frequency 2) CL (load capacitance) 30pF 3) CS (shunt capacitance) 7pF 4) RS (equivalent shunt resistance) 75 5) Drive level: 10mW 6) Frequency tolerance: 0.005% (suggested)
VDD
TRAP F.F. INTERNAL TRAP ACKNOWLEDGE
FIGURE 8. TRAP AND RESET IN CIRCUIT
The TRAP interrupt is special in that is disables interrupts, but preserves the previous interrupt enable status. Performing the first RIM instruction following a TRAP interrupt allows you to determine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM instructions provide current interrupt enable status. Performing a RIM instruction following INTR, or RST 5.5-7.5 will provide current interrupt enable status, revealing that interrupts are disabled. The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM, and SIM sets the SOD data. Driving the X1 and X2 Inputs You may drive the clock inputs of the HS-80C85RH with a crystal, an LC tuned circuit, an RC network, or an external clock source. The driving frequency may be any value from DC to 4MHz and must be twice the desired internal clock frequency. The following guidelines should be observed when a crystal is used to drive the HS-80C85RH clock input:
1. A 20pF capacitor should be connected from X2 to ground to assure oscillator start-up at the correct frequency.
A parallel-resonant LC circuit may be used as the frequencydetermining network for the HS-80C85RH, providing that its frequency tolerance of approximately 10% is acceptable. The components are chosen from the formula: 1 f= 2 L (Cext + Cint) To minimize variations in frequency, it is recommended that you choose a value for Cext that is at least twice that of Cint, or 30pF. The use of an LC circuit is not recommended for frequencies higher than approximately 4MHz. An RC circuit may be used as the frequency-determining network for the HS-80C85RH if maintaining a precise clock frequency is of no importance. Variations in the on-chip timing generation can cause a wide variation in frequency when using the RC mode. Its advantage is its low component cost. The driving frequency generated by the circuit shown is approximately 3MHz. It is not recommended that frequencies greatly higher or lower than this be attempted. Figure 9 shows the recommended clock driver circuits. For driving frequencies up to and including 4MHz you may supply the driving signal to X1 and leave X2 open-circuited (Figure 9D).
X1 1 REXT = 10M 2
80C85RH 20pF CINT = 15pF -6K 2 1
X1
80C85RH
20pF
X2
X2
a.) QUARTZ CRYSTAL CLOCK DRIVER
c.) RC CIRCUIT CLOCK DRIVER
LOW TIME > 60ns X1 1 LEXT CEXT 2 X2 CINT = 15pF 80C85RH
X1

X2 Left Floating
X2
b.) LC TUNED CIRCUIT CLOCK DRIVER
d.) 0-4MHz INPUT FREQUENCY EXTERNAL CLOCK DRIVER CIRCUIT
FIGURE 9. CLOCK DRIVER CIRCUITS
Spec Number 13
518054
HS-80C85RH
HS-80C85RH Caveats
1. An important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule also applies to inputs connected to a tri- state bus. The need for external pull-up resistors during tri-state bus conditions is eliminated by the presence of regenerative latches on the following HS-80C85RH output pins: AD0-AD7, A8-A15, and IO/M. Figure 10 depicts an output and corresponding regenerative latch. When the output driver assumes the high impedance state, the latch holds the bus in whatever logic state (high or low) it was before the tri-state condition. A transient drive current of approximately 1.0mA at 0.5 VDD for 10nsec is required to switch the latch. Thus, CMOS device inputs connected to the bus are not allowed to float during tri-state conditions. 2. The RD and WR pins of the HS-80C85RH contain internal dynamic pull-up transistors to avoid spurious selection of memory devices when the RD and WR pins assume the high impedance state. This eliminates the need for external resistive pull-ups on these pins. 3. The RESET IN and X1 inputs on the HS-80C85RH are schmit trigger inputs. This eliminates the possibility of internal oscillations in response to slow rise time input signals at these pins. 4. A high frequency bypass capacitor of approximately 0.1 F should be connected between VDD and GND to shunt power supply transients. 5. The HS-80C85RH is functional within 10 input clock cycles after application of power (assuming that reset has been asserted from power-on). Start up conditions in the crystal controlled oscillator mode must also account for the characteristics of the oscillator.
System Interface The HS-80C85RH family includes memory components, which are directly compatible to the HS-8OC8SRH CPU. For example, a system consisting of the three radiationhardened chips, HS-80C85RH, HS-81C56RH, and HS-83C55RH will have the following features:
1. 2K Bytes ROM 2. 256 Bytes RAM 3. 1 Timer/Counter 4. 4 8-bit I/O Ports 5. 1 6-bit I/O Port 6. 4 Interrupt Levels 7. Serial In/Serial Out Ports
This minimum system, using the standard I/O technique is as shown in Figure 12. In addition to standard 1/0, the memory mapped I/O offers an efficient I/O addressing technique. With this technique, an area of memory address space is assigned for I/O address, thereby, using the memory address for I/O manipulation. Figure 13 shows the system configuration of Memory Mapped I/O using HS-80C85RH. The HS-80C85RH CPU can also interface with the standard radiation-hardened memory that does not have the multiplexed address/data bus. It will require use of the HS-82C12RH (8-bit latch) as shown in Figure 14.
VSS VDD
OUTPUT DRIVER
OUTPUT PIN REGENERATIVE LATCH
FIGURE 10. OUTPUT DRIVER AND LATCH FOR PINS ADO-AD7, A8-A15 AND IO/M.
X1 X2 RESET IN HOLD TRAP HLDA RST 7.5 SOD RST 6.5 HS-80C85RH SID RST 5.5 S1 INTR RESET INTA ADDR/ S0 OUT RDY CLK ADDR DATA ALE RD WR IO/M (8) (8)
VSS VDD
Generating An HS-80C85RH Wait State If your system requirements are such that slow memories or peripheral devices are being used, the circuit shown in Figure 11 may be used to insert one WAIT state in each HS-80C85RH machine cycle. The D flip-flops should be chosen so that:
1. CLK is rising edge-triggered 2. CLEAR is low-level active.
HS-81C56RH
CE WR RD ALE
PORT A PORT B
(8) (8) (6)
DATA/ PORT ADDR C IN IO/M TIMER RESET OUT IOW RD ALE CE HS-83C55RH
The READY line is used to extend the read and write pulse lengths so that the 80C85RH can be used with slow memory. HOLD causes the CPU to relinquish the bus when it is through with it by floating the Address and Data Buses.
CLEAR CLK "D" F/F D 80C85RH CLK OUTPUT Q TO 80C85RH READY INPUT Q
PORT A
(8)
A0-10 DATA/ ADDR PORT IO/M B RESET RDY IOR CLK
(8) VDD
ALE VDD
CLK "D" F/F D
VSS VDD
ALE and CLK (OUT) should be buffered if CLK
input of latch exceeds 80C85RH IOL or IOH.
VDD
Optional Connection
FIGURE 11. GENERATION OF A WAIT STATE FOR HS-80C85RH CPU.
FIGURE 12. HS-80C85RH MINIMUM SYSTEM (STANDARD I/O TECHNIQUE)
Spec Number 14
518054
HS-80C85RH
A8-15 AD0-7 ALE HS-80C85RH RD WR IO/M CLK RESET OUT READY
VDD
TIMER
RESET
IN WR RD ALE CE
AD0-7
IO/M
IOW
AD0-7
CLK
CE
TIMER OUT
HS-81C56RH (RAM + I/O + COUNTER/TIMER)
HS-83C55RH (ROM +I/O)
(6)
(8)
(8)
(8)
(8)
RDY
A8-10
IO/M
ALE
RST
RD
Optional Connection
FIGURE 13. HS-80C85RH MINIMUM SYSTEM (MEMORY MAPPED I/O)
VSS VDD
TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA ADDR (8)
X1
HOLD HLDA SOD HS-80C85RH SID S1 RESET S0 ADDR/ DATA ALE RD WR IO/M OUT RDY CLK (8) IO/M (CS) WR RD
X2
RESET IN
HS-82C12RH
STANDARD MEMORY DATA
ADDR (CS)
CLK (16) RESET IO/M (CS) WR RD I/O PORTS, CONTROLS
DATA STANDARD I/O ADDR
VDD VDD VDD
FIGURE 14. HS-80C85RH SYSTEM (USING STANDARD MEMORIES)
Spec Number 15
518054
HS-80C85RH
Basic System Timing The HS-80C85RH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of address on the Data Bus. Figure 15 shows an instruction fetch, memory read and I/O write cycle (as would occur during processing of the OUT instruction). Note that during the I/O write and read cycle that the I/O port address is copied on both the upper and lower half of the address. There are seven possible types of machine cycles. Which of these seven takes place is defined by the status of the three status lines (lO/M, S1, S0) and the three control signals (RD, WR, and INTA). (See Table 10.) The status lines can be used as advanced controls (for device selection, for example), since they become active at the T1 state, at the outset of each machine cycle. Control lines RD and WR are used as command lines since they become active when the transfer of data is to take place.
TABLE 10. HS-80C85RH MACHINE CYCLE CHART STATUS MACHINE CYCLE Opcode Fetch (OF) Memory Read (MR) Memory Write (MW) I/O Read I/O Write (IOR) (IOW) IO/M S1 0 0 0 1 1 1 DAD Ack. of RST, TRAP HALT 0 1 TS 1 1 0 1 0 1 1 1 0
M1 CLK T1 T2 T3 T4 T1
A machine cycle normally consists of three T states, with the exception of OPCODE FETCH, which normally has either four or six T states (unless WAIT or HOLD states are forced by the receipt of READY or HOLD inputs). Any T state must be one of ten possible states, shown in Table 11.
TABLE 11. HS-80C85RH MACHINE STATE CHART MACHINE STATE T1 T2 TWAIT T3 T4 T5 T6 STATUS & BUSES CONTROL
S1, S0 IO/M A8-15 AD0-7 RD,WR INTA ALE X X X X 1 1 1 X 0 X X X X X 0 0 0 TS TS TS X X X X X X X TS TS TS X X X X TS TS TS TS TS TS 1 X X X 1 1 1 TS TS TS 1 X X X 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
CONTROL S0 RD WR INTA 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 1 1
TRESET THALT THOLD 0 = Logic "0" 1 = Logic "1" instruction.
TS = High Impedance X = Unspecified
ALE not generated during 2nd and 3rd machine cycles of DAD IO/M = 1 during T4, T6 of INA machine cycle.
Acknowledge (INA) of INTR Bus Idle (BI)
TS TS
M2 T2 T3 T1
M3 T2 T3 T
A8-A15
PCH (HIGH ORDER ADDRESS)
(PC + 1)H
IO PORT
AD0-7
PCL (LOW ORDER DATA FROM ADDRESS) MEMORY (INSTRUCTION)
(PC+1)L DATA TO MEMORY OR PERIPHERAL
IO PORT DATA FROM MEMORY (I/O PORT ADDRESS)
ALE
RD
WR
IO/M
STATUS
S1-S0 (FETCH)
10 (READ)
01 WRITE
11
FIGURE 15. 80C85RH BASIC SYSTEM TIMING
Spec Number 16
518054
HS-80C85RH Metallization Topology
DIE DIMENSIONS: 229 mils x 240 mils x 14 mils 1 mil METALLIZATION: Type: SiAl Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA
Metallization Mask Layout
HS-80C85RH
(37) CLOCK OUT (3) RESET OUT (36) RESET IN (35) READY (34) IO/M (33) S1 (32) RD (31) WR AD0 (12) (30) ALE (29) S0 (28) A15 (27) A14 (26) A13 (25) A12 AD3 (15) AD4 (16) AD5 (17) AD6 (18) AD7 (19) GND (20) A10 (23) A8 (21) A9 (22) A11 (24)
(39) HOLD
TRAP (6) RST 7.5 (7) RST 6.5 (8) RST 5.5 (9) INTR (10) INTA (11)
AD1 (13) AD2 (14)
(38) HLDA
(40) VDD
(4) SOD
(5) SID
(2) X2
(1) X1
Spec Number 17
518054
HS-80C85RH Packaging
1
E N A A D b E1 L C Q E2 A S1
K42.A TOP BRAZED 42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES SYMBOL A b b1 c c1 D E MIN 0.017 0.017 0.007 0.007 1.045 0.630 0.530 MAX 0.100 0.025 0.023 0.013 0.010 1.075 0.650 0.680 0.550 MILLIMETERS MIN 0.43 0.43 0.18 0.18 26.54 16.00 13.46 MAX 2.54 0.64 0.58 0.33 0.25 27.31 16.51 17.27 13.97 NOTES 3 3 11 8.89 1.65 0.04 42 8 6 Rev. 0 6/17/94
e
c1
LEAD FINISH
E1 E2
BASE METAL b1 M M (b) SECTION A-A
(c)
e k L Q S1 M N
0.050 BSC 0.320 0.045 0.000 42 0.350 0.065 0.0015 -
1.27 BSC
8.13 1.14 0.00 -
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 11. The basic lead spacing is 0.050 inch (1.27mm) between center lines. Each lead centerline shall be located within 0.005 inch (0.13mm) of its exact longitudinal position relative to lead 1 and the highest numbered (N) lead.
Spec Number 18
518054
HS-80C85RH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Spec Number 19

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